Field of the Disclosure
The present disclosure relates to a memory device, and in particular, it relates to a resistive random access memory (RRAM) cell structure and a 3D crossbar array thereof.
Description of the Related Art
As the functionality of integrated chips increases, the need for more memory also increases. Designers have been looking to decrease the size of the memory element and stack more memory elements in a unit area to achieve greater capacity and lower costs per bit. In the past few decades, the aggressive shrinkage of memory elements is due to advancements in lithography techniques. Flash memory has been widely used as large-capacity, inexpensive nonvolatile memory which can store data even when it is powered off. In addition, flash memory can achieve high density by using 3D arrays, such as by using vertical NAND memory cell stacking. However, it has been found that further miniaturization of flash memory is limited due to the increasing cost.
Designers are now looking at next-generation nonvolatile memories such as MRAMs (Magnetoresistive Random Access Memory), PCRAMs (Phase Change Random Access Memory), CBRAMs (Conductive Bridging Random Access Memory) and RRAMs (Resistive Random Access Memory), to increase writing speeds and decrease power consumption. Among the nonvolatile memories, the RRAM has the greatest potential to replace flash memories due to its simple structure, simple crossbar array and suitability for low-temperature fabrication. A unit element of the RRAM is composed of only an insulator with two metal electrodes.
Although the RRAM crossbar array architecture is simple, there are still many problems that need to be overcome for fabrication, especially for three-dimensional (3D) crossbar array architectures. Without a vertical 3D architecture, the RRAM will most likely not be able to compete with 3D NAND memories in terms of bit cost for mass data storage.
The RRAM crossbar array architectures based on resistive switching elements theoretically allows for the smallest cell size of 4F2 where F is the minimum feature size, and the low-temperature fabrication enables stacking of memory arrays three-dimensionally, for unprecedented high-integration density. However, in the 1R structure (having a resistive element only), undesired sneak current that flows through neighboring unselected memory cells significantly deteriorates the read margin, and limits the maximum size of the crossbar array to below 64 bits. This problem can be mitigated by additional nonlinear selection devices in series with the resistive switching elements. Some memory cell structures, such as one diode-one resistor (1D1R), one bipolar selector-one resistor (1S1R), one MOSFET transistor-one resistor (1T1R), and one bipolar junction transistor-one resistor 1BJT1R memory cell structures, have been developed. Among the memory cell structures, the 1T1R and 1BJT1R memory cell structures are undesirable because of the complicated and high-temperature fabrication requirements of MOSFETs and BJTs, while the complementary resistive switching (CRS) memory cell structure suffers from the issue of destructive read. Hence, the 1D1R and 1S1R memory cell structures appear to be the leading contenders for the 3D crossbar array architectures.
However, the 3D crossbar array architectures of the 1D1R or 1S1R memory cell structures still cannot be successfully fabricated. The 1D1R and 1S1R memory cell structures are basically formed of a metal-insulator-metal-insulator-metal (MIMIM) structure. FIG. 1 shows an exemplary scheme of an ideal RRAM 3D crossbar array architecture including 1D1R and 1S1R memory cell stacked structures. The MIMIM structure of the 1D1R or 1S1R memory cell structures is formed between the conductive lines 102 and 104 along the horizontal longitude 106 perpendicular to sidewalls of the conductive lines 102 and 104. However, the RRAM 3D crossbar array architecture is usually formed within a semiconductor substrate. After the formation of the conductive lines 102, lithography processes can only be performed from the direction 110. Performing the lithography processes from the direction 110 will not form the patterned metal layer 108 shown in FIG. 1, which eliminates application for the 3D crossbar array architectures through the 1D1R and 1S1R memory cell structures.